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Novel Low Power Logic Gates using Sleepy Techniques

Vijaylaxmi C Kalal, Ravikumar K. I, Chaitrali V. Pawar

The subthreshold voltage is declining in successive nanometre technologies and has an associated effect of enhanced leakage current. This causes the static (leakage) power to be a vital portion of total power dissipation in a VLSI circuit. Two novel circuit techniques for leakage current reduction in logic gates are presented in this work. The proposed circuit techniques are applied to universal NAND and NOR logic gates. The performance of these low leak gates is compared with earlier CMOS circuit leakage minimization techniques applied to these gates. The novel ultra low leak technique provides maximum leakage current reduction with lower output levels. Low Power State Retention- LPSR technique provides lower leakage power and the state of the gate can also be retained in sleep mode. The proposed low leak gates are designed and simulated using cadence design tools for 90 nm CMOS process technology. The leakage power for the novel methods during sleep mode is found to be better with and without state retention as compared to earlier best known techniques. The dynamic power dissipation for the proposed techniques is least.