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High speed, Low power N/ (N+1) prescaler using TSPC and E-TSPC: A survey

Nemitha B, Pradeep Kumar B.P

One of the important functional blocks in frequency synthesizers is the high speed dual modulus prescaler. Prescaler determines how fast the frequency synthesizer is. The bottleneck of the dual modulus prescaler design is that it operates at the highest frequencies and consumes more power than any other circuit blocks of the synthesizer. Reduction of power consumption and delay is very important for high speed low power applications. This paper gives an idea about the different techniques that are used to reduce the power consumption and avoid delay of prescaler. The different approaches towards design of N/(N+1) prescaler using true single phase clock(TSPC) flip-flop and Extended true single phase clock (ETSPC) flip-flop and different logic gates are embedded between the flip-flops to achieve two ratios and also to reduce the switching power and short circuit power in the prescaler is analyzed.