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Bus Energy Minimization for a Serial Link by Modified Embedded Transition Inversion Coding

J. Jenifa, C.Jacob Ebbipeni, V.Monisha

In all type of electronic circuits, reducing the energy dissipation is one of the major topics of interest. In bus interconnect lines, the dynamic power dissipation contributes a significant fraction in the overall power dissipation. Hence, the main objective of VLSI designers is to minimize the power dissipation, switching activity, on the interconnect lines. A modified Embedded Transition Coding Scheme reduces the number of bus lines in conventional parallel-line bus by multiplexing each m-bits onto a single line is proposed. The advantage of Serial Line Bus is that they have fewer lines, reducing crosstalk and area. Serializing parallel buses tends to increase bit transition and power dissipation. The proposed Embedded Transition Inversion Coding method uses an efficient encoding and decoding technique in order to minimize the transition activity and power consumption in serial links. In previous method a transition indication bit is added in every data word to represent a inversion indication. This extra bit increases the number of transmitted bits, number of bit transitions and power dissipation. This proposed coding scheme is used to solve the issue of the extra indication bit. This scheme eliminates the need of sending an extra bit by embedding the inversion information in the phase difference between the clock and the encoded data.In this proposed method Alexander Phase Detector is replaced by Half Rate Phase Detector. The proposed system is simulated by using Xilinx 13.1 software to get efficient output. The proposed system result analysis shows better than the existing method.