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An Experimental Implementation of Convolution Encoder and Viterbi Decoder by FPGA Emulation

Shraddha Shukla, Nagendra Sah

Error-correcting convolution codes prove to be a powerful methodology to limit the effects of noise in digital data transmission. Convolution Encoding with Viterbi decoding is a powerful Forward Error Control (FEC) technique that is a proven mechanism in which the transmitted signal remains uncorrupted mainly by Additive white Gaussian Noise residing inside a channel. In this work, a Convolution Encoder and Viterbi Decoder with a constraint length of 3 and code rate of ½ have been developed on xc3s250e-4-pq208 Spartan 3E board. VHDL language is used as a design entry. It is simulated and synthesized using Modelsim 6.4a and Xilinx 8.1i ISE respectively. With this way of configuration, the FPGA is capable of operating by itself as a Convolutional encoder or Viterbi decoder. Hence, it gains benefit through the reuse of the same hardware